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Design PWM circuit

The questions below are due on Wednesday April 01, 2020; 11:59:00 PM.
 
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Pulse-width modulation (PWM) is a modulation technique that allows to control the power supplied to electrical devices, especially when those devices act like inductors or capacitors. It can also be used to turn a digital signal into an analog signal by feeding a PWM signal into an RC circuit. Let's do some analysis and design of a PWM system.

In a PWM digital-to-analog converter (DAC), the Teensy outputs a square wave of digital HI and digital LO, with a variable duty cycle:

duty \, cycle = \frac{t_{ON}}{T}

The information about the analog level we want to ultimately achieve (the "commanded voltage") is encoded in that variable duty cycle. As shown here:

The duty cycle determines the average value of the signal, which is:

v_{AVE} = duty \, cycle \cdot V_{cc}

Remember that for the Teensy V_{cc} is 3.3 V. To extract out the average value, we feed the signal into a simple RC network as shown above. Once the system has reached a periodic steady state (i.e. it reaches a cycling state where the voltages repeat with some time period), we obtain an output:

v_C(t) = v_{C,ave} + v_r(t)

where v_r(t) is the ripple voltage, which has amplitude v_{ripple} as shown in the plot above.

Two things we care about in designing R and C are the ripple amplitude and the response time. In the periodic steady state, the response to the PWM signal can be obtained by splitting the PWM signal into two signals:

v_s = v_{AVE} + v_{AC}

These are shown here:

v_{AVE} is a constant voltage, and the circuit will respond to that input with v_c = v_{AVE}. In the ideal case, the circuit output v_c would be simply equal to v_{AVE} at all times. Unfortunately, in the real world, the circuit will also respond to v_{AC}.

Let's figure out the amplitude of v_{ripple}, magnified in the plot below:

From this plot, v_{ripple} = v_2 - v_1 = v_2 - v_3. The periodic steady state will occur when the voltage gain between t_1 and t_2 equals the voltage loss between t_2 and t_3. Put another way, periodic steady state will occur when v_3 = v_1. Answer the following questions assuming the system has reached the periodic steady state, and that the duty cycle is 0.5.

Use Vcc for V_{cc}, v1 for v_1, v2 for v_2, and D for D as needed in the questions below.

Determine an expression for v_2 in terms of v_1, V_{cc}, and/or the factor D, where D=e^{-(\delta t/\tau)} and \delta t = t_2 - t_1 = t_3 - t_2.
v_2=

Determine an expression for v_3 in terms of v_2, V_{cc}, and/or the factor D, where D=e^{-(\delta t/\tau)} and \delta t = t_2 - t_1 = t_3 - t_2.
v_3=

Determine an expression for v_{ripple} in terms of V_{cc} and/or the factor D, where D=e^{-(\delta t/\tau)} and \delta t = t_2 - t_1 = t_3 - t_2.
v_{ripple}=

In setting up the system to minimize ripple, then, we have control over both \tau (via the external circuit) and T (via setting the internal PWM frequency on the Teensy). The default T is ~2 ms (correspond to a frequency of 488.28 Hz, to be exact). This can be increased up to 12 MHz if desired.

Assuming T = 2 ms and 50% duty cycle, what is the minimum \tau (in ms) to obtain a \le 10 mV ripple voltage.
\tau \ge

Of course, larger \tau will lead to even smaller ripple, but the downside is that the analog voltage cannot change as quickly. The time constant that determines how long it takes to reach a new commanded analog voltage is the same \tau. Thus, a larger \tau results in a system that is less responsive.

Assume instead of a 50% duty cycle, to create an analog voltage of 0.5 \cdot 3.3 V = 1.65 V, we want to create a square wave analog voltage that goes from 1 V to 3 V.

What duty cycle corresponds to 1 V? duty cycle =

What duty cycle corresponds to 3 V? duty cycle =

Assuming that T = 2 ms, to create a 3 V analog voltage, how much time (in ms) is the Teensy output pin voltage at 3.3 V during every 2 ms interval?
t_{ON} =

Using the minimum \tau we designed above puts a limit on how quickly we can change the analog voltage that results from the PWM signal. Imagine we start with a duty cycle that, in the periodic steady state, would yield a 1 V commanded analog voltage. Then we switch to a duty cycle that would yield a 3 V commanded voltage, and then switch back to the duty cycle for 1 V. We then repeat this process. To achieve a repeating periodic pattern, we will transition between different duty cycles once the signal has changed by 95% of the total possible change.

Consider the rise time and fall time of the signal for this situation. The inverse of the sum of the two times corresponds to our maximal switching rate in Hz, as in the figure below:

What is the maximal rate (in Hz) at which we can switch back and forth between 1 V to 3 V under these conditions?
switching rate =

Not very fast! We can speed things up by either allowing more ripple or increasing the PWM frequency. The latter, though, decreases the resolution of the analog voltage that we can create.