Home / Exercises 03 / Back to the DAC

Back to the DAC

The questions below are due on Wednesday February 26, 2020; 11:59:00 PM.
You are not logged in.

If you are a current student, please Log In for full access to the web site.
Note that this link will take you to an external site (https://shimmer.csail.mit.edu) to authenticate, and then you will be redirected back to this page.

In Lab 2 we built a DAC using a resistive ladder. In this problem we'll revisit that circuit and examine its performance using some of the new tools we have learned.


In lab we used discrete resistors (out of the cabinet) to build the resistor network. Standard resistors have a 5% tolerance, which means a resistor of nominal value R can vary from between R-0.05R to R+0.05R. How does this affect our DAC?

Consider the topology of our DAC, which is provided again below:

Assume that the resistors R can vary from R+\Delta R to R-\Delta R, and the 2R resistors can vary from 2R+2\Delta R to 2R-2\Delta R. We want to determine under what conditions the output voltage V_O will be minimal.

A good way to approach this question is to recast the circuit as a Thevenin equivalent to the left of port A-A', as show below:

where here R_L is nominally 2R, and R_{TH} must be determined from the original circuit. Under what conditions of R_{TH} and R_L will the output voltage V_O be minimal?

Enter expressions for R_{TH} and R_L that provide the minimum V_O under the conditions that the resistors R and 2R can vary as above. Enter \Delta R as DR.

R_{TH} =
R_L =

###Thevenin equivalent

Now, going back to the situation where the resistor values are exactly R and 2R, determine the Thevenin equivalent of the entire circuit (now including the right-most 2R), looking into port B-B':

In particular, determine expressions for V_{TH} and R_{TH} that are correct under all combinations of the voltage sources being zero or non-zero.

As always, enter V_1 as V1, etc.

R_{TH} =
V_{TH} =

###Driving a load

A DAC is almost always used to create an analog voltage that will be connected to a load, e.g., the element we want to drive. In lab 2 this was a piezo speaker. It was specifically chosen because it's equivalent resistance -- also known as its input resistance -- is large. Driving loads with large input resistances is typically easier than driving smaller resistances.

Assuming you chose to create your DAC from a mid-range set of resistances, aka R = 10 k\Omega, what is the minimum load resistance that one can drive such that one loses no more than 50% of the voltage supplied by the DAC circuit?

Enter the minimum load resistance [in \Omega].